1. Field of the Invention
The present invention relates to a storage tester, in particular, to a storage tester which can operate a respective test for storage differently through a plurality of sequence control modules controlling a plurality of SATA/SAS/PCIe.
2. Description of the Related Art
A hard disc (HDD) is generally known and used as mass digital media storage until the present.
However, as recently lowered is the price of NAND flash semiconductor device which can keep storing data without power and store the largest capacity of storage among semiconductors having memory function, a mass digital media storage such as SSD using semiconductors having memory function is newly emerging.
The function of SSD is realized through a SSD tester, a conventional SSD tester for testing the said SSD is shown in FIG. 1.
As shown in FIG. 1, a host terminal 100, network 200, a communication interface unit 300, memory 400, an embedded processor 500, a data engine unit 600, and SATA/SAS/PCIe interface unit 700 comprise a single FPGA or one chip.
Herein, when the host terminal 100 sends macro command for testing storage 10 through network 200 and the communication interface unit 300 to the embedded processor 500, the embedded processor 500 writes data in the storage 10 by sending command to the data engine unit 600 and the SATA/SAS/PCIe interface unit 700, etc., reads written data, compares those with expected values, determines pass/fail of storage 10 and transmits the result to the host terminal 100.
Also, the communication interface unit 300 serves for interface enabling to transceive data among the host terminal 100, one of the embedded processor 500, the data engine unit 600 and SATA/SAS/PCIe interface unit 700.
And also the embedded processor 500 as a microprocessor realized inside FPGA or ASIC chip controls the data engine unit 600, SATA/SAS/PCIe interface unit 700, etc., and serves for controlling in order to test storage using the data engine unit 600, SATA/SAS/PCIe interface unit 700, etc.
Also, the data engine unit 600 generates pattern data, command data, and etc. on real time, and reads data from the storage 10 on real time, and compares those with pattern data generated in the data engine and stores in fail memory.
And SATA/SAS/PCIe interface unit 700 enables data to be recorded in and read from the storage 10 using interface needed for corresponding to the storage interface.
On the other hand, there is prior art related to a device for testing storage filed or disclosed such as Korea patent publication No. 10-2010-0114697 (hereinafter called “cited reference”), and etc.
The cited reference as mentioned above comprises a storage interface unit for managing interface with the storage; user interface unit for receiving test condition from user for storage test; a test pattern generation unit for generating test pattern for storage test corresponding to the test condition received from the user; and a test control unit for controlling the storage test through the test pattern.
In the prior art including the cited reference, a single embedded processor is used to control a plurality of SATA/SAS/PCIe interface unit. Accordingly the embedded processor has too much burden for controlling a plurality of SATA/SAS/PCIe interface units and it takes longer time for processing.
It doesn't become a big problem in transmitting the same control command simultaneously to a plurality of SATA/SAS/PCIe interface units and checking individual condition of each SATA/SAS/PCIe interface unit.
However, if different control instructions are transmitted to a plurality of SATA/SAS/PCIe interface units respectively at different point of time using a single embedded processor, test requires more time.
Thus, in order to solve this problem, a plurality of embedded processors can be used in transmitting respectively different control instructions to a plurality of SATA/SAS/PCIe interface unit, or it can be implemented to design a sequence control module for controlling a plurality of SATA/SAS/PCIe interface units using user logic by using a single embedded processor and the user logic.
Here, a method controlling a plurality of SATA/SAS/PCIe interface units using a plurality of embedded processors is difficult to implement in practice because the method requires the large number of gates in embedded processors, and additional peripherals and the size of logic is increased.